Using an ATM Interconnect as a High Performance I/O Backplane†

We present the design of an ATM-based interconnect that serves as a high speed packet-switched equivalent of an I/O bus in a workstation/server. By effectively “extending” an external ATM network into the desk-area, the interconnect also functions as a high performance host-network interface. The prototype interconnect, which we are building as part of an ARPA sponsored gigabit local ATM testbed, boasts an aggregate sustained bidirectional data rate in excess of a gigabit per second. The interconnect design, which is targeted specifically for multimedia workstations/servers, employs a single custom VLSI chip called the ATM Port Interconnect Controller (APIC); by daisy-chaining a number of these chips, and connecting each to an I/O device, we can support the uninterrupted flow of continuous media data from device to device, as well as from a device to the network and vice-versa.